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Capacitor bank voltage rise and parallel resonance

ΔV=QcSsc×100h=SscQcfr=hf0
where
ΔV
steady-state voltage rise (%)
Qc
capacitor bank rating (Mvar)
Ssc
short-circuit level at the bank (MVA)
h
parallel resonance harmonic order
fr
resonant frequency (Hz)
f0
system frequency (Hz)
Explain this equation

Estimates the voltage step when a capacitor bank is switched in and the harmonic order at which the bank resonates with the source inductance. Use both when siting a pf-correction or reactive-compensation bank.

Ssc represents the source reactance: a stiff network has high Ssc and low reactance. Qc represents the bank’s capacitive admittance. The ratio of the two sets both the voltage rise and the resonant point.

The reactive current from the bank flowing through the source reactance raises the voltage by Qc/Ssc in per unit. Parallel resonance happens where the source reactance, which rises with frequency, equals the capacitive reactance, which falls with it; that crossover is at h = √(Ssc/Qc).

Sense check: 350 kvar on a 10 MVA busbar gives a 3.5 % rise and resonance near the 5th harmonic (h ≈ 5.3). Quadrupling the bank halves h.

Watch out: a resonance near 5, 7, 11 or 13 will amplify the harmonic currents of drives and rectifiers. Check at both minimum and maximum fault level.

Estimates the voltage step when a shunt capacitor bank is switched in, and the harmonic order at which the bank resonates in parallel with the source inductance.

Hz

Enter your values to see the result.

Good to know

Use the minimum and maximum credible fault levels at the bank: the resonant order moves as the network changes. A bank with series detuning reactors (tuning order h = 1/√p for a reactor of p per unit: a 7 % reactor tunes to about 3.8 × f0, a 5.67 % reactor to 4.2 × f0) is inductive above its tuning frequency, so it cannot form a parallel resonance with the source at the 5th or higher harmonics; this simple formula does not apply to detuned banks. The voltage-step figure is the quantity compared with ENA P28 step-change limits.

Common mistake

Using the upstream grid fault level instead of the fault level at the capacitor bus. Downstream of a transformer, the transformer impedance dominates and lowers Ssc, so the resonance falls towards the 5th or 7th harmonic.

Limits

Assumes the source is purely inductive and the bank is the only capacitance; cable capacitance, loads (which add damping) and other banks are ignored. Use a frequency scan for design.

Sources

For competent high-voltage engineers. Results are calculations from the published methods shown and depend entirely on the data you enter. They are not a substitute for a system study, manufacturer data, the applicable standards and Engineering Recommendations, or your organisation’s safety rules. Never use a result to justify working on or near live HV equipment.

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